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"VHDL synthesis description portability: The need for Level synthesis subsets."

Manfred Selz, Wolfgang Ecker, Eugenio Villar (1996)

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DOI: 10.1016/1383-7621(96)00017-3

access: closed

type: Journal Article

metadata version: 2020-05-19

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  dblp key:
  - journals/jsa/SelzEV96
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  - https://dblp.org/rec/journals/jsa/SelzEV96
Manfred Selz, Wolfgang Ecker, Eugenio Villar:
VHDL synthesis description portability: The need for Level synthesis subsets. J. Syst. Archit. 42(2): 105-116 (1996)

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