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"A robust and real-time DNN-based multi-baseline stereo accelerator in FPGAs."

Yu Zhang et al. (2023)

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DOI: 10.1016/J.SYSARC.2023.102966

access: closed

type: Journal Article

metadata version: 2023-10-12

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  - journals/jsa/ZhangZLMC23
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  - https://dblp.org/rec/journals/jsa/ZhangZLMC23
Yu Zhang, Yi Zheng, Yehua Ling, Haitao Meng, Gang Chen:
A robust and real-time DNN-based multi-baseline stereo accelerator in FPGAs. J. Syst. Archit. 143: 102966 (2023)

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