"A circuit design of intelligent cache DRAM with automatic write-back ..."

Kazutami Arimoto et al. (1991)

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DOI: 10.1109/4.75055

access: closed

type: Journal Article

metadata version: 2025-02-26

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Kazutami Arimoto, Mikio Asakura, Hideto Hidaka, Yoshio Matsuda, Kazuyasu Fujishima:
A circuit design of intelligent cache DRAM with automatic write-back capability. IEEE J. Solid State Circuits 26(4): 560-565 (1991)

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