"A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input ..."

Harijot Singh Bindra et al. (2018)

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DOI: 10.1109/JSSC.2018.2820147

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type: Journal Article

metadata version: 2020-08-30

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Harijot Singh Bindra, Chris E. Lokin, Daniël Schinkel, Anne-Johan Annema, Bram Nauta:
A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise. IEEE J. Solid State Circuits 53(7): 1902-1912 (2018)

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