"The 65-nm 16-MB Shared On-Die L3 Cache for the Dual-Core Intel Xeon ..."

Jonathan Chang et al. (2007)

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DOI: 10.1109/JSSC.2007.892185

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type: Journal Article

metadata version: 2023-02-10

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Jonathan Chang, Ming Huang, Jonathan Shoemaker, John Benoit, Szu-Liang Chen, Wei Chen, Siufu Chiu, Raghuraman Ganesan, Gloria Leong, Venkata Lukka, Stefan Rusu, Durgesh Srivastava:
The 65-nm 16-MB Shared On-Die L3 Cache for the Dual-Core Intel Xeon Processor 7100 Series. IEEE J. Solid State Circuits 42(4): 846-852 (2007)

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