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"A 4.5-GHz 130-nm 32-KB L0 cache with a leakage-tolerant self reverse-bias ..."

Steven Hsu et al. (2003)

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DOI: 10.1109/JSSC.2003.810058

access: closed

type: Journal Article

metadata version: 2022-04-20

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Steven Hsu, Atila Alvandpour, Sanu Mathew, Shih-Lien Lu, Ram K. Krishnamurthy, Shekhar Borkar:
A 4.5-GHz 130-nm 32-KB L0 cache with a leakage-tolerant self reverse-bias bitline scheme. IEEE J. Solid State Circuits 38(5): 755-761 (2003)

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