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"A 1.5-ns cycle-time 18-kb pseudo-dual-port RAM with 9K logic gates."
Masato Iwabuchi et al. (1994)
- Masato Iwabuchi, Masami Usami, Masamori Kashiyama, Takashi Oomori, Shigeharu Murata, Toshiro Hiramoto, Takashi Hashimoto, Yasuhiro Nakajima:
A 1.5-ns cycle-time 18-kb pseudo-dual-port RAM with 9K logic gates. IEEE J. Solid State Circuits 29(4): 419-425 (1994)
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