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"An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O ..."

Kyu-Hyoun Kim et al. (2007)

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DOI: 10.1109/JSSC.2006.888297

access: closed

type: Journal Article

metadata version: 2023-07-28

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  - https://dblp.org/rec/journals/jssc/KimCKPJKPKCCK07
Kyu-Hyoun Kim, Hoeju Chung, Woo-Seop Kim, Moon-Sook Park, Young-Chan Jang, Jinyoung Kim, Hwan-Wook Park, Uksong Kang, Paul W. Coteus, Joo-Sun Choi, Changhyun Kim:
An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme. IEEE J. Solid State Circuits 42(1): 193-200 (2007)

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