"A 1.6-Gb/s/pin double data rate SDRAM with wave-pipelined CAS latency control."

Sang-Bo Lee et al. (2005)

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DOI: 10.1109/JSSC.2004.837983

access: closed

type: Journal Article

metadata version: 2022-03-02

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Sang-Bo Lee, Seong-Jin Jang, Jin-Seok Kwak, Sang-Jun Hwang, Young-Hyun Jun, Soo-In Cho, Chil-Gee Lee:
A 1.6-Gb/s/pin double data rate SDRAM with wave-pipelined CAS latency control. IEEE J. Solid State Circuits 40(1): 223-232 (2005)

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