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"A 12-Bit 1.6, 3.2, and 6.4 GS/s 4-b/Cycle Time-Interleaved SAR ADC With ..."

Jae-Won Nam et al. (2018)

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DOI: 10.1109/JSSC.2018.2808244

access: closed

type: Journal Article

metadata version: 2020-08-30

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  - https://dblp.org/rec/journals/jssc/NamHZC18
Jae-Won Nam, Mohsen Hassanpourghadi, Aoyang Zhang, Mike Shuo-Wei Chen:
A 12-Bit 1.6, 3.2, and 6.4 GS/s 4-b/Cycle Time-Interleaved SAR ADC With Dual Reference Shifting and Interpolation. IEEE J. Solid State Circuits 53(6): 1765-1779 (2018)

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