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"A 5.6-ns random cycle 144-Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface."

Harold Pilo et al. (2003)

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DOI: 10.1109/JSSC.2003.818141

access: closed

type: Journal Article

metadata version: 2022-04-20

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Harold Pilo, Darren Anand, John Barth, Steve Burns, Phil Corson, Jim Covino, Steve Lamphier:
A 5.6-ns random cycle 144-Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface. IEEE J. Solid State Circuits 38(11): 1974-1980 (2003)

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