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"A 1.6-GB/s data-rate 1-Gb synchronous DRAM with hierarchical square-shaped ..."

Narumi Sakashita et al. (1996)

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DOI: 10.1109/JSSC.1996.542309

access: closed

type: Journal Article

metadata version: 2022-07-18

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  - https://dblp.org/rec/journals/jssc/SakashitaNSOSYT96
Narumi Sakashita, Yasuhiko Nitta, Ken'ichi Shimomura, Fumihiro Okuda, Hiroki Shimano, Satoshi Yamakawa, Masaki Tsukude, Kazutami Arimoto, Shinji Baba, Shinji Komori, Kazuo Kyuma, Akihiko Yasuoka, Haruhiko Abe:
A 1.6-GB/s data-rate 1-Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture. IEEE J. Solid State Circuits 31(11): 1645-1655 (1996)

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