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"A 5-GByte/s data-transfer scheme with bit-to-bit skew control for ..."

Takashi Sato et al. (1999)

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DOI: 10.1109/4.760375

access: closed

type: Journal Article

metadata version: 2022-10-02

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Takashi Sato, Yoji Nishio, Toshio Sugano, Yoshinobu Nakagome:
A 5-GByte/s data-transfer scheme with bit-to-bit skew control for synchronous DRAM. IEEE J. Solid State Circuits 34(5): 653-660 (1999)

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