![](https://dblp.org/img/logo.ua.320x120.png)
![](https://dblp.org/img/dropdown.dark.16x16.png)
![](https://dblp.org/img/peace.dark.16x16.png)
Остановите войну!
for scientists:
![search dblp search dblp](https://dblp.org/img/search.dark.16x16.png)
![search dblp](https://dblp.org/img/search.dark.16x16.png)
default search action
"An eight-bit prefetch circuit for high-bandwidth DRAM's."
Toshio Sunaga et al. (1997)
- Toshio Sunaga, Koji Hosokawa, Yutaka Nakamura, Manabu Ichinose, Yasuyuki Igarashi:
An eight-bit prefetch circuit for high-bandwidth DRAM's. IEEE J. Solid State Circuits 32(1): 105-110 (1997)
![](https://dblp.org/img/cog.dark.24x24.png)
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.