"Reprogrammable Redundancy for SRAM-Based Cache Vmin Reduction ..."

Brian Zimmer et al. (2017)

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DOI: 10.1109/JSSC.2017.2715798

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type: Journal Article

metadata version: 2020-08-30

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Brian Zimmer, Pi-Feng Chiu, Borivoje Nikolic, Krste Asanovic:
Reprogrammable Redundancy for SRAM-Based Cache V_min Reduction in a 28-nm RISC-V Processor. IEEE J. Solid State Circuits 52(10): 2589-2600 (2017)

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