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"Compiling gate RC models into a top level simulation model for ..."

Zainalabedin Navabi (1991)

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DOI: 10.1016/0141-9331(91)90110-2

access: closed

type: Journal Article

metadata version: 2021-05-25

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Zainalabedin Navabi:
Compiling gate RC models into a top level simulation model for rough timing analysis of VLSI circuits. Microprocess. Microsystems 15(6): 313-320 (1991)

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