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"An AES crypto chip using a high-speed parallel pipelined architecture."

Seong-Moo Yoo et al. (2005)

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DOI: 10.1016/J.MICPRO.2004.12.001

access: closed

type: Journal Article

metadata version: 2020-05-18

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  - https://dblp.org/rec/journals/mam/YooKPB05
Seong-Moo Yoo, Deen Kotturi, W. David Pan, John Blizzard:
An AES crypto chip using a high-speed parallel pipelined architecture. Microprocess. Microsystems 29(7): 317-326 (2005)

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