"Logic-in-Memory VLSI circuit for Fully Parallel Nearest Pattern Matching ..."

Takahiro Hanyu, Shunichi Kaeriyama, Michitaka Kameyama (2005)

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type: Journal Article

metadata version: 2020-04-02

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Takahiro Hanyu, Shunichi Kaeriyama, Michitaka Kameyama:
Logic-in-Memory VLSI circuit for Fully Parallel Nearest Pattern Matching Based on Floating-Gate-MOS Pass-Transistor Logic. J. Multiple Valued Log. Soft Comput. 11(5-6): 619-632 (2005)

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