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"1-bit full adder design using next generation semiconductor devices and ..."

S. Lakshmanachari et al. (2024)

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DOI: 10.1007/S13198-023-02181-Y

access: closed

type: Journal Article

metadata version: 2024-05-07

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S. Lakshmanachari, Sadulla Shaik, G. S. R. Satyanarayana, Inapudi Vasavi, Vallabhuni Vijay, Chandra Shaker Pittala:
1-bit full adder design using next generation semiconductor devices and performance benchmarking at low supply voltages. Int. J. Syst. Assur. Eng. Manag. 15(3): 950-956 (2024)

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