"A novel reconfigurable architecture of a DSP processor for efficient ..."

Amitabha Sinha et al. (2013)

> Home

Details and statistics

DOI: 10.1145/2490302.2490304

access: closed

type: Journal Article

metadata version: 2020-07-30

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/sigarch/SinhaSAC13
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/sigarch/SinhaSAC13
Amitabha Sinha, Mitrava Sarkar, Soumojit Acharyya, Suranjan Chakraborty:
A novel reconfigurable architecture of a DSP processor for efficient mapping of DSP functions using field programmable DSP arrays. SIGARCH Comput. Archit. News 41(2): 1-8 (2013)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.