"Logic Synthesis for Interpolant Circuit Compaction."

Gianpiero Cabodi et al. (2019)

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DOI: 10.1109/TCAD.2018.2808229

access: closed

type: Journal Article

metadata version: 2021-09-16

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  - https://dblp.org/rec/journals/tcad/CabodiCPPV19
Gianpiero Cabodi, Paolo Camurati, Marco Palena, Paolo Pasini, Danilo Vendraminetto:
Logic Synthesis for Interpolant Circuit Compaction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(2): 380-384 (2019)

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