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"A Novel Hierarchical Circuit LUT Model for SOI Technology for Rapid ..."

Sitansusekhar Roymohapatra et al. (2020)

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DOI: 10.1109/TCAD.2019.2907879

access: closed

type: Journal Article

metadata version: 2020-09-24

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Sitansusekhar Roymohapatra, Ganesh R. Gore, Akanksha Yadav, Mahesh B. Patil, Krishnan S. Rengarajan, Subramanian S. Iyer, Maryam Shojaei Baghini:
A Novel Hierarchical Circuit LUT Model for SOI Technology for Rapid Prototyping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(5): 1073-1083 (2020)

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