![](https://dblp.org/img/logo.ua.320x120.png)
![](https://dblp.org/img/dropdown.dark.16x16.png)
![](https://dblp.org/img/peace.dark.16x16.png)
Остановите войну!
for scientists:
![search dblp search dblp](https://dblp.org/img/search.dark.16x16.png)
![search dblp](https://dblp.org/img/search.dark.16x16.png)
default search action
"A 12.8-Gb/s Quarter-Rate Transmitter Using a 4: 1 Overlapped Multiplexing ..."
Joo-Hyung Chae et al. (2019)
- Joo-Hyung Chae
, Hyeongjun Ko, Jihwan Park, Suhwan Kim
:
A 12.8-Gb/s Quarter-Rate Transmitter Using a 4: 1 Overlapped Multiplexing Driver Combined With an Adaptive Clock Phase Aligner. IEEE Trans. Circuits Syst. II Express Briefs 66-II(2): 372-376 (2019)
![](https://dblp.org/img/cog.dark.24x24.png)
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.