"A 28-nm FD-SOI 8T Dual-Port SRAM for Low-Energy Image Processor With ..."

Haruki Mori et al. (2019)

> Home

Details and statistics

DOI: 10.1109/TCSI.2018.2885536

access: closed

type: Journal Article

metadata version: 2025-01-19

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tcas/MoriNKKTYIKY19
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tcas/MoriNKKTYIKY19
Haruki Mori, Tomoki Nakagawa, Yuki Kitahara, Yuta Kawamoto, Kenta Takagi, Shusuke Yoshimoto, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 28-nm FD-SOI 8T Dual-Port SRAM for Low-Energy Image Processor With Selective Sourceline Drive Scheme. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(4): 1442-1453 (2019)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.