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"Low-Latency Digit-Serial and Digit-Parallel Systolic Multipliers for Large ..."

Jeng-Shyang Pan, Chiou-Yng Lee, Pramod Kumar Meher (2013)

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DOI: 10.1109/TCSI.2013.2264694

access: closed

type: Journal Article

metadata version: 2022-12-07

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Jeng-Shyang Pan, Chiou-Yng Lee, Pramod Kumar Meher:
Low-Latency Digit-Serial and Digit-Parallel Systolic Multipliers for Large Binary Extension Fields. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(12): 3195-3204 (2013)

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