"Synthesis of Ternary Logic Circuits Using 2: 1 Multiplexers."

Chetan Vudadha et al. (2018)

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DOI: 10.1109/TCSI.2018.2838258

access: closed

type: Journal Article

metadata version: 2020-05-22

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Chetan Vudadha, Ajay Surya, Saurabh Agrawal, M. B. Srinivas:
Synthesis of Ternary Logic Circuits Using 2: 1 Multiplexers. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(12): 4313-4325 (2018)

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