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"An At-Speed Test Technique for High-Speed High-order Adder by a 6.4-GHz ..."

Yu-Shun Wang et al. (2012)

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DOI: 10.1109/TCSI.2012.2206503

access: closed

type: Journal Article

metadata version: 2020-05-22

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Yu-Shun Wang, Min-Han Hsieh, James Chien-Mo Li, Charlie Chung-Ping Chen:
An At-Speed Test Technique for High-Speed High-order Adder by a 6.4-GHz 64-bit Domino Adder Example. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(8): 1644-1655 (2012)

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