"Synchronous Non-Volatile Logic Gate Design Based on Resistive Switching ..."

Weisheng Zhao et al. (2014)

> Home

Details and statistics

DOI: 10.1109/TCSI.2013.2278332

access: closed

type: Journal Article

metadata version: 2022-10-02

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tcas/ZhaoMDZPKBADMQRRC14
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tcas/ZhaoMDZPKBADMQRRC14
Weisheng Zhao, Mathieu Moreau, Erya Deng, Yue Zhang, Jean-Michel Portal, Jacques-Olivier Klein, Marc Bocquet, Hassen Aziza, Damien Deleruyelle, Christophe Muller, Damien Querlioz, Nesrine Ben Romdhane, Dafine Ravelosona, Claude Chappert:
Synchronous Non-Volatile Logic Gate Design Based on Resistive Switching Memories. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(2): 443-454 (2014)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.