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"A Methodology for the Design of Fault Tolerant Parallel Digital ..."
Zhen Gao et al. (2023)
- Zhen Gao, Jiajun Xiao, Qiang Liu, Anees Ullah, Pedro Reviriego:
A Methodology for the Design of Fault Tolerant Parallel Digital Channelizers on SRAM-FPGAs. IEEE Trans. Circuits Syst. I Regul. Pap. 70(5): 2003-2015 (2023)
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