"An Efficient Fault-Tolerant Instruction Decoder for RISC-V Based Dual-Core ..."

Satyam Shukla et al. (2023)

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DOI: 10.1109/TCSI.2023.3315604

access: closed

type: Journal Article

metadata version: 2024-10-06

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Satyam Shukla, Utkarsh, Md Azam, Kailash Chandra Ray:
An Efficient Fault-Tolerant Instruction Decoder for RISC-V Based Dual-Core Soft-Processors. IEEE Trans. Circuits Syst. I Regul. Pap. 70(12): 4816-4825 (2023)

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