"A Low-Cost 0.00063-mm2, 0.44-pJ/b, 2-Gb/s All-Digital Fully ..."

Ankur Bal et al. (2022)

> Home

Details and statistics

DOI: 10.1109/TCSII.2022.3185499

access: closed

type: Journal Article

metadata version: 2022-10-18

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tcasII/BalSKD22
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tcasII/BalSKD22
Ankur Bal, Rupesh Singh, Aradhana Kumari, Vikas Dhanda:
A Low-Cost 0.00063-mm², 0.44-pJ/b, 2-Gb/s All-Digital Fully Synthesizable CDR for Serial Links Using Single-Phase Input Clock. IEEE Trans. Circuits Syst. II Express Briefs 69(10): 4073-4077 (2022)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.