"Efficient ASIC Architecture for Low Latency Classic McEliece Decoding."

Daniel Fallnich et al. (2024)

> Home

Details and statistics

DOI: 10.46586/TCHES.V2024.I2.403-425

access: open

type: Journal Article

metadata version: 2024-06-08

- view
  - electronic edition via DOI (open access)
  authority control:
- export record
  dblp key:
  - journals/tches/FallnichLZG24
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tches/FallnichLZG24
Daniel Fallnich, Christian Lanius, Shutao Zhang, Tobias Gemmeke:
Efficient ASIC Architecture for Low Latency Classic McEliece Decoding. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2024(2): 403-425 (2024)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.