"A FPGA-Based Systolic Array Prototype Implementing the Quadrant ..."

M. Ch. Karra, M. P. Bekakos (2006)

> Home

Details and statistics

DOI: 10.1007/S11227-006-6633-X

access: closed

type: Journal Article

metadata version: 2020-05-22

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tjs/KarraB06
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tjs/KarraB06
M. Ch. Karra, M. P. Bekakos:
A FPGA-Based Systolic Array Prototype Implementing the Quadrant Interlocking Factorization Method. J. Supercomput. 37(3): 319-331 (2006)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.