"Rtl design flaws revisited: a data-driven study of systematic bug patterns ..."

Xiankai Meng et al. (2025)

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DOI: 10.1007/S11227-025-07811-9

access: closed

type: Journal Article

metadata version: 2025-11-19

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Xiankai Meng, Xiang Ji, Guangda Zhang, Jiayu He, Deheng Yang, Fangshu Chen, Jiahui Wang, Chengcheng Yu, Xinlin Zhao, Jiang Wu:
Rtl design flaws revisited: a data-driven study of systematic bug patterns in Verilog code. J. Supercomput. 81(14): 1321 (2025)

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