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"A VLSI Layout for a Pipelined Dadda Multiplier"
Peter R. Cappello, Kenneth Steiglitz (1983)
- Peter R. Cappello, Kenneth Steiglitz:
A VLSI Layout for a Pipelined Dadda Multiplier. ACM Trans. Comput. Syst. 1(2): 157-174 (1983)
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