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"Logical Effort Framework for CNFET-Based VLSI Circuits for Delay and Area ..."

Muhammad Ali, Mohammad A. Ahmed, Malgorzata Chrzanowska-Jeske (2019)

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DOI: 10.1109/TVLSI.2018.2880322

access: closed

type: Journal Article

metadata version: 2021-02-19

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Muhammad Ali, Mohammad A. Ahmed, Malgorzata Chrzanowska-Jeske:
Logical Effort Framework for CNFET-Based VLSI Circuits for Delay and Area Optimization. IEEE Trans. Very Large Scale Integr. Syst. 27(3): 573-586 (2019)

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