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"Parallel interleaver design and VLSI architecture for low-latency MAP ..."

Rostislav (Reuven) Dobkin, Michael Peleg, Ran Ginosar (2005)

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DOI: 10.1109/TVLSI.2004.842916

access: closed

type: Journal Article

metadata version: 2020-03-11

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Rostislav (Reuven) Dobkin, Michael Peleg, Ran Ginosar:
Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders. IEEE Trans. Very Large Scale Integr. Syst. 13(4): 427-438 (2005)

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