"A Low-Jitter ADPLL via a Suppressive Digital Filter and an ..."

Hsuan-Jung Hsu, Shi-Yu Huang (2011)

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DOI: 10.1109/TVLSI.2009.2030410

access: closed

type: Journal Article

metadata version: 2020-03-11

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Hsuan-Jung Hsu, Shi-Yu Huang:
A Low-Jitter ADPLL via a Suppressive Digital Filter and an Interpolation-Based Locking Scheme. IEEE Trans. Very Large Scale Integr. Syst. 19(1): 165-170 (2011)

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