"A 10-Gb/s CML I/O Circuit for Backplane Interconnection in 0.18-µm ..."

Min-Sheng Kao et al. (2009)

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DOI: 10.1109/TVLSI.2009.2016726

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type: Journal Article

metadata version: 2020-03-11

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Min-Sheng Kao, Jen-Ming Wu, Chih-Hsing Lin, Fanta Chen, Ching-Te Chiu, Shawn S. H. Hsu:
A 10-Gb/s CML I/O Circuit for Backplane Interconnection in 0.18-µm CMOS Technology. IEEE Trans. Very Large Scale Integr. Syst. 17(5): 688-696 (2009)

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