![](https://dblp.org/img/logo.ua.320x120.png)
![](https://dblp.org/img/dropdown.dark.16x16.png)
![](https://dblp.org/img/peace.dark.16x16.png)
Остановите войну!
for scientists:
![search dblp search dblp](https://dblp.org/img/search.dark.16x16.png)
![search dblp](https://dblp.org/img/search.dark.16x16.png)
default search action
"A 36-Gb/s 2× Half-Baud-Rate Adaptive Receiver in 28-nm CMOS."
Yi-Hao Lan, Shen-Iuan Liu (2024)
- Yi-Hao Lan, Shen-Iuan Liu
:
A 36-Gb/s 2× Half-Baud-Rate Adaptive Receiver in 28-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 32(7): 1263-1272 (2024)
![](https://dblp.org/img/cog.dark.24x24.png)
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.