"Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST."

Martin Omaña et al. (2017)

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DOI: 10.1109/TVLSI.2016.2572606

access: closed

type: Journal Article

metadata version: 2022-11-20

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Martin Omaña, Daniele Rossi, Filippo Fuzzi, Cecilia Metra, Chandra Tirumurti, Rajesh Galivanche:
Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 238-246 (2017)

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