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"Simultaneous On-Chip Bus Synthesis and Voltage Scaling Under Random ..."

Sujan Pandey, Manfred Glesner (2007)

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DOI: 10.1109/TVLSI.2007.903924

access: closed

type: Journal Article

metadata version: 2020-03-11

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  - https://dblp.org/rec/journals/tvlsi/PandeyG07
Sujan Pandey, Manfred Glesner:
Simultaneous On-Chip Bus Synthesis and Voltage Scaling Under Random On-Chip Data Traffic. IEEE Trans. Very Large Scale Integr. Syst. 15(10): 1111-1124 (2007)

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