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"Glitch-Optimized Circuit Blocks for Low-Power High-Performance Booth ..."

Anuradha Chathuranga Ranasinghe, Sabih H. Gerez (2020)

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DOI: 10.1109/TVLSI.2020.3009239

access: closed

type: Journal Article

metadata version: 2020-09-19

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  - https://dblp.org/rec/journals/tvlsi/RanasingheG20
Anuradha Chathuranga Ranasinghe, Sabih H. Gerez:
Glitch-Optimized Circuit Blocks for Low-Power High-Performance Booth Multipliers. IEEE Trans. Very Large Scale Integr. Syst. 28(9): 2028-2041 (2020)

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