"Modeling subthreshold SOI logic for static timing analysis."

Alexandre Valentian et al. (2004)

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DOI: 10.1109/TVLSI.2004.827602

access: closed

type: Journal Article

metadata version: 2020-03-11

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Alexandre Valentian, Olivier Thomas, Andrei Vladimirescu, Amara Amara:
Modeling subthreshold SOI logic for static timing analysis. IEEE Trans. Very Large Scale Integr. Syst. 12(6): 662-669 (2004)

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