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"Instruction buffering for nested loops in low-power design."

Chi Ta Wu, Ang-Chih Hsieh, TingTing Hwang (2006)

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DOI: 10.1109/TVLSI.2006.878348

access: closed

type: Journal Article

metadata version: 2020-03-11

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  - https://dblp.org/rec/journals/tvlsi/WuHH06
Chi Ta Wu, Ang-Chih Hsieh, TingTing Hwang:
Instruction buffering for nested loops in low-power design. IEEE Trans. Very Large Scale Integr. Syst. 14(7): 780-784 (2006)

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