"FPGA Fault Tolerant Arithmetic Logic: A Case Study Using Parallel-Prefix ..."

David H. K. Hoe, L. P. Deepthi Bollepalli, Chris D. Martinez (2013)

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DOI: 10.1155/2013/382682

access: open

type: Journal Article

metadata version: 2019-06-02

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David H. K. Hoe, L. P. Deepthi Bollepalli, Chris D. Martinez:
FPGA Fault Tolerant Arithmetic Logic: A Case Study Using Parallel-Prefix Adders. VLSI Design 2013: 382682:1-382682:10 (2013)

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