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ORCIDVLSI Design, Volume 2013
Volume 2013, 2013
- Shadi Traboulsi, Valerio Frascolla
, Nils Pohl, Josef Hausner, Attila Bilgic:
Energy-Efficient Hardware Architectures for the Packet Data Convergence Protocol in LTE-Advanced Mobile Terminals. 369627:1-369627:15 - Mauro Olivieri, Antonio Mastrandrea:
A General Design Methodology for Synchronous Early-Completion-Prediction Adders in Nano-CMOS DSP Architectures. 785281:1-785281:12 - Yu-Cheng Fan, Yi-Feng Chiang:
Discrete Wavelet Transform on Color Picture Interpolation of Digital Still Camera. 738057:1-738057:9 - Hiroki Iwaizumi, Shingo Yoshizawa, Yoshikazu Miyanaga:
A High-Speed and Low-Energy-Consumption Processor for SVD-MIMO-OFDM Systems. 625019:1-625019:10 - A. Kishore Kumar, D. Somasundareswari, V. Duraisamy, T. Shunbaga Pradeepa:
Design of Low Power Multiplier with Energy Efficient Full Adder Using DPTAAL. 157872:1-157872:9 - Carna Radojicic, Christoph Grimm, Florian Schupfer, Michael Rathmair:
Verification of Mixed-Signal Systems with Affine Arithmetic Assertions. 239064:1-239064:14 - Diego Javier Reinoso Chisaguano, Minoru Okada:
Low Complexity Submatrix Divided MMSE Sparse-SQRD Detection for MIMO-OFDM with ESPAR Antenna Receiver. 206909:1-206909:11 - Hou-Ming Chen, Robert C. Chang, Kuang-Hao Lin:
A High-Efficiency Monolithic DC-DC PFM Boost Converter with Parallel Power MOS Technique. 643293:1-643293:7 - Huan Ren, Shantanu Dutt:
Fast and Near-Optimal Timing-Driven Cell Sizing under Cell Area and Leakage Power Constraints Using a Simplified Discrete Network Flow Algorithm. 474601:1-474601:15 - Liyuan Liu, Dongmei Li, Zhihua Wang:
A 0.6-V to 1-V Audio Delta-Sigma Modulator in 65 nm CMOS with 90.2 dB SNDR at 0.6-V. 353080:1-353080:9 - Ting-Li Chu, Sin-Hong Yu, Chorng-Sii Hwang:
High-Accuracy Programmable Timing Generator with Wide-Range Tuning Capability. 803616:1-803616:6 - Tinoosh Mohsenin, Houshmand Shirani-mehr, Bevan M. Baas:
LDPC Decoder with an Adaptive Wordwidth Datapath for Energy and BER Co-Optimization. 913018:1-913018:14 - Ching-Lung Su, Tse-Min Chen, Kuo-Hsuan Wu:
A Prototype-Based Gate-Level Cycle-Accurate Methodology for SoC Performance Exploration and Estimation. 529150:1-529150:10 - Yu-Ming Hsiao, Miin-Shyue Shiau, Kuen-Han Li, Jing-Jhong Hou, Heng-Shou Hsu, Hong-Chong Wu, Don-Gey Liu:
Design a Bioamplifier with High CMRR. 210265:1-210265:5 - B. Ramkumar, Harish M. Kittur:
Faster and Energy-Efficient Signed Multipliers. 495354:1-495354:12 - Masahide Hatanaka, Toru Homemoto, Takao Onoye:
Architecture and Implementation of Fading Compensation for Dynamic Spectrum Access Wireless Communication Systems. 967370:1-967370:9 - Francesco Colonna, Mariagrazia Graziano, Mario Roberto Casu, Xiaolu Guo, Maurizio Zamboni:
Hardware Acceleration of Beamforming in a UWB Imaging Unit for Breast Cancer Detection. 861691:1-861691:11 - Tai-Hsuan Wu, Azadeh Davoodi, Jeffrey T. Linderoth:
Power-Driven Global Routing for Multisupply Voltage Domains. 905493:1-905493:12 - Anupam Chattopadhyay:
Ingredients of Adaptability: A Survey of Reconfigurable Processors. 683615:1-683615:18 - Bisrat Tafesse, Venkatesan Muthukumar:
Framework for Simulation of Heterogeneous MpSoC for Design Space Exploration. 936181:1-936181:16 - Ching-Hwa Cheng:
Design Example of Useful Memory Latency for Developing a Hazard Preventive Pipeline High-Performance Embedded-Microprocessor. 425105:1-425105:10 - Zheng Xie, Doug A. Edwards:
Computational Performance Optimisation for Statistical Analysis of the Effect of Nano-CMOS Variability on Integrated Circuits. 984376:1-984376:22 - Ahmed Elhossini, Shawki Areibi, Robert D. Dony:
Architecture Exploration Based on GA-PSO Optimization, ANN Modeling, and Static Scheduling. 624369:1-624369:22 - David H. K. Hoe, L. P. Deepthi Bollepalli, Chris D. Martinez:
FPGA Fault Tolerant Arithmetic Logic: A Case Study Using Parallel-Prefix Adders. 382682:1-382682:10 - Shipra Upadhyay, Rajendra Kumar Nagaria, Ram Awadh Mishra:
Low-Power Adiabatic Computing with Improved Quasistatic Energy Recovery Logic. 726324:1-726324:9 - Mao-Hsu Yen, Chu Yu, Horng-Ru Liao, Chin-Fa Hsieh:
A Generic Three-Sided Rearrangeable Switching Network for Polygonal FPGA Design. 103473:1-103473:15 - Dinesh P. Mehta, Carl Shetters, Donald W. Bouldin:
Meta-Algorithms for Scheduling a Chain of Coarse-Grained Tasks on an Array of Reconfigurable FPGAs. 249592:1-249592:13
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