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"Scalability Analysis for Conservative Simulation of Logical Circuits."

Jörg Keller, Thomas Rauber, Bernd Rederlechner (1999)

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DOI: 10.1155/1999/14802

access: open

type: Journal Article

metadata version: 2023-05-08

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  - https://dblp.org/rec/journals/vlsi/KellerRR99
Jörg Keller, Thomas Rauber, Bernd Rederlechner:
Scalability Analysis for Conservative Simulation of Logical Circuits. VLSI Design 9(3): 219-235 (1999)

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