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ORCID"A Phase-Locked Loop with 30% Jitter Reduction Using Separate Regulators."
Tzung-Je Lee, Chua-Chin Wang (2008)
- Tzung-Je Lee, Chua-Chin Wang:
A Phase-Locked Loop with 30% Jitter Reduction Using Separate Regulators. VLSI Design 2008: 512946:1-512946:8 (2008)
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