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"A Dynamically Reconfigurable Video Compression Scheme Using FPGAs with ..."

Seetharaman Ramachandran, S. Srinivasan (2002)

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DOI: 10.1080/1065514021000012138

access: open

type: Journal Article

metadata version: 2023-05-08

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  - journals/vlsi/Ramachandran002
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  - https://dblp.org/rec/journals/vlsi/Ramachandran002
Seetharaman Ramachandran, S. Srinivasan:
A Dynamically Reconfigurable Video Compression Scheme Using FPGAs with Coarse-grain Parallelism. VLSI Design 15(2): 521-528 (2002)

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